It's a whole bunch of hard IP containing both cores, and you only get a bunch of AXI interfaces into/out of the FPGA fabric. Nothing in the system interconnect looks to be configurable.
My clueless guess is, it's something with the L2-310 cache controller.
The article doesn't mention anything about what FPGA image is loaded into the thing.
My guess would be that you can choose how to connect the CPU cores to the cache controller, you might want to run the CPUs independently.
> My guess would be that you can choose how to connect the CPU cores to the cache controller,
Not in this device, cf. https://docs.altera.com/r/docs/683126/21.2/cyclone-v-hard-pr...
It's a whole bunch of hard IP containing both cores, and you only get a bunch of AXI interfaces into/out of the FPGA fabric. Nothing in the system interconnect looks to be configurable.
My clueless guess is, it's something with the L2-310 cache controller.
This is about the hard macros in Altera Cyclone V FPGA.
I suspect the issue is in how Altera configured the IP. They may simply have disabled some part to save on area.
In the equivalent AMD/Xilinx parts (Zynq), you connect up all the hard IP macros using the FPGA fabric.
If the hard cores are configured with incorrect cache coherency options you may not be able to correct the issue in fpga fabric.
But this is pure speculation, I haven't checked Cyclone V documentation myself.